The present invention relates to methods and apparatus for floating body charge monitoring in partially depleted silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) circuits.
Silicon-on-insulator (SOI) technology is an enhanced silicon technology currently being utilized to increase the performance of digital logic circuits. By utilizing SOI technology, designers can increase the speed of digital logic integrated circuits or can reduce their overall power consumption. These advances in technology enable the development of more complex and faster integrated circuits that operate with less power.
A SOI transistor suffers from one inherent flaw. The floating body of the SOI transistor can develop a body charge over time. The amount of such floating body charge depends upon the potentials at the source, drain and gate of the SOI transistor. The maximum amount of charging occurs when the gate is completely turned off and both the source and drain electrodes are biased at the highest voltage supply Vdd. Given enough time and/or potential at the source and drain, the body charge of the SOI transistor will eventually reach a saturation level. If a switching activity occurs for that device, a transient parasitic bipolar current exists in conjunction with the normal device drain current. The transient parasitic bipolar current causes the well known first cycle performance degradation. In multiplexer style SOI circuit topologies, such timing behavior variation is particularly troublesome.
U.S. Pat. No. 6,078,058 issued Jun. 20, 2000 to Hsu et al. and assigned to the present assignee discloses an SOI floating body charge monitor circuit and method for discharging the body of a monitored SOI device through first and second discharge circuits. The second discharge circuit is selectively activated when the body potential of the monitored SOI device is at a level such that the body charge of the monitored SOI device cannot be discharged entirely through the first discharge circuit within normal operating cycle time allowances. The subject matter of the above-identified patent is incorporated herein by reference.
A need exists for an improved and effective mechanism for monitoring excess body charges in partially depleted SOI devices.
A principal object of the present invention is to provide an improved mechanism for monitoring excess body charges in partially depleted SOI CMOS devices. Other important objects of the present invention are to provide methods and apparatus for monitoring excess body charges in partially depleted SOI devices substantially without negative effect and that overcome many of the disadvantages of prior art arrangements.
In brief, methods and apparatus are provided for monitoring excess body charges in partially depleted SOI CMOS devices. Apparatus for floating body charge monitoring in partially depleted silicon-on-insulator (SOI) CMOS circuits includes a monitor core circuit for conditionally generating an intentional bipolar discharge current. A current mirroring multiplier is coupled to the monitor core circuit for amplifying the intentional bipolar discharge current and generating a state disturb current. A state setting latch is coupled to the current mirroring multiplier for determining and setting a condition for a discharge action.